A digitally-calibrated 2-stage cyclic ADC for a 33-Mpixel 120-fps Super High-Vision CMOS image sensor

The effectiveness of a proposed digital calibration technique for a 2-stage single-ended cyclic ADC suitable for a 33-Mpixel 120-fps Super High-Vision (SHV) CMOS image sensor is demonstrated by implementing an experimental chip. A calibration algorithm improves the nonlinearity of the ADC by correcting errors generated in the ADC due to capacitor mismatch, finite gain error, incomplete settling error, reference voltage error, and offset error. The measured output of the ADC designed and fabricated as an experimental chip was digitally calibrated by using the algorithm. The DNL was improved to +0.20/-0.27 LSB from +0.22/-0.83 LSB and the INL was improved to +5.8/-5.4 LSB from +8.4/-6.0 LSB. In addition to the improvement of the output characteristics, the calibration results confirm that the power consumption and layout area of the ADC can be designed smaller than those determined by the ADC resolution.