On the design consideration of ultra-thin-film SOI MOSFETs

The authors present an alternative thin-film SOI (silicon-on-insulator) design that achieves low source-substrate injection efficiency to enable device operation at 5-V drain bias without transistor latch or anomalous breakdown. As an alternative to LDD (lightly doped drain) implants, two relatively simple alterations to the conventional SOI MOSFET were incorporated. Two features in the proposed structure distinguish it from past thin-film SOI designs: salicide source/drain electrodes that extend fully to the insulating material and complete gate overlapping of source/drain implants. The effectiveness of the proposed design in prohibiting the parasitic bipolar action from becoming catastrophic is shown. The simulated output characteristic reveals a breakdown voltage approaching 7 V for the transistor, a significant improvement over the result reported by G.A. Armstrong et al. (1991)