Design and technology of fine-grained sleep transistor circuits in ultra-deep sub-micron CMOS technologies

The reduction of leakage currents in deep sub-micron CMOS is a challenging design criterion. The block level sleep transistor scheme is an established strategy to suppress static power consumption in unused circuit blocks. Suspending small logic blocks for even very short time intervals is the next step to cope with continuously increasing leakage currents. A design methodology for the power switch is demonstrated for a 16 bit multiply accumulate unit. A straightforward strategy to determine the minimum power-down time is demonstrated. A charge recycling scheme reduces the minimum power-down time by reducing the switching overhead. A double switch scheme reduces the on-current during block activation significantly and enables a faster block activation.