DocumentCode
1894012
Title
Mixed body-bias techniques with fixed Vt and Ids generation circuits
Author
Sumita, Masaya ; Sakiyama, Shiro ; Kinoshita, Masayoshi ; Araki, Yuta ; Ikeda, Yuichiro ; Fukuoka, Kouhei
Author_Institution
Matsushita Electr. Ind. Co. Ltd. (Panasonic), Nagaokakyo, Japan
fYear
2005
fDate
9-11 May 2005
Firstpage
233
Lastpage
234
Abstract
In sub 1 V CMOS VLSIs, the authors proposed a new body bias generation circuits in which Ids and Vt of pMOS/nMOS become always fixed. The mixed body bias techniques result in positive temperature dependence of the delay, 85% reduction of the delay variation, and 75% improvement of power consumption of SRAM on a mobile processor.
Keywords
MIS devices; SRAM chips; integrated circuit design; low-power electronics; power consumption; CMOS VLSI; SRAM; generation circuits; mixed body bias techniques; mobile processor; nMOS; pMOS; positive temperature dependence; CMOS process; Character generation; Circuit testing; Delay; Intrusion detection; MOS devices; Random access memory; Semiconductor device measurement; Temperature distribution; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on
Print_ISBN
0-7803-9081-4
Type
conf
DOI
10.1109/ICICDT.2005.1502638
Filename
1502638
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