Title :
Records of the 2003 IEEE International Workshop on Memory Technology, Design and Testing
Abstract :
The following topics are dealt with: application specific DRAMs; cost optimum embedded DRAM design; memory test generation for DRAM defects; linked faults analysis in RAMs; reducing test time of embedded SRAMs; testability-driven optimizer and wrapper generator for embedded memories; ITRS commodity roadmap; electrical simulation model for the Chalcogenide phase-change memory cell.
Keywords :
DRAM chips; SRAM chips; digital simulation; embedded systems; logic testing; dynamic RAM; electrical simulation model; embedded DRAM design; embedded SRAM; embedded memories; linked faults analysis; memory cell; memory technology; memory test generation; random access memory; static RAM; wrapper generator; DRAM chips; Logic circuit testing; SRAM chips;
Conference_Titel :
Memory Technology, Design and Testing, 2003. Records of the 2003 International Workshop on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7695-2004-9
DOI :
10.1109/MTDT.2003.1222353
