Integration and packaging plateaus of processor performance

Integration and packaging performance limits are refined in the context of computer systems. In particular, limits of computer performance under various packaging, architectural, organizational, and design techniques (e.g. gate-array versus custom) are explored. It is concluded that fully integrated processors can have modest electrical signal I/O requirements because the frequency of signals crossing their pins can be several times less than that of the on-chip clock frequency. In order to exploit emerging technologies without high levels of integration, advanced volumetric packaging techniques will still be very important