Title :
CMOS inverter current and delay model incorporating interconnect effects
Author :
Hafed ; Rumin, N.
Author_Institution :
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada
fDate :
31 May-3 Jun 1998
Abstract :
We present a new model for predicting the switching current and delay in a CMOS inverter with an RC load. The model exploits the ability of an inverter model to predict accurately the current peak time, tm, as a function of inverter size, input slope and capacitive load. An iterative procedure computes the effective capacitance presented by the RC load, using an empirical model for the output voltage of the RC load driven by a reference inverter. Not only is the resulting model accurate but computationally efficient as well so that a two to three order speed up over HSPICE is achieved
Keywords :
CMOS logic circuits; capacitance; circuit analysis computing; delays; integrated circuit interconnections; integrated circuit modelling; iterative methods; logic gates; CMOS inverter current model; CMOS inverter delay model; RC load; capacitive load; current peak time; effective capacitance; input slope; interconnect effects; inverter size; iterative procedure; switching current; Capacitance; Current supplies; Delay effects; Integrated circuit interconnections; Inverters; MOS devices; Pulse shaping methods; Semiconductor device modeling; Shape; Voltage;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.705218
