Implementation of Haar Transform with PDDA Architecture for Flexible Scales

In this paper, a novel approach to the flexible scales of Haar wavelet transform in FPGAs is proposed, which could be achieved by only a single parallel dynamic distributed arithmetic (PDDA) FIR architecture with some pipelining registers. In addition, floating-point system is adopted to provide higher resolution over a large dynamic range. Furthermore, the scheme is mapped into a Xilinx Virtex5 FPGA chip. The synthesis results demonstrate it performs faster and consumes less resource under the same precision compared with conventional methods.