Title :
Path resizing based on incremental technique
Author :
Cremoux, S. ; Azemard, N. ; Auvergne, D.
Author_Institution :
Lab. d´´Inf., de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
fDate :
31 May-3 Jun 1998
Abstract :
Based on an incremental path search algorithm, this paper addresses the problem of longest combinational paths selection for performance optimization at the physical level. A realistic evaluation of gate delay and controlled sizing techniques are used to manage the circuit path sizing alternatives, such as delay or power/area constraints. The efficiency of this technique is demonstrated and also illustrated on several ISCAS´85 benchmark circuits. A comparison is given between sizing alternatives to local optimization steps controlled by specific indicators
Keywords :
circuit layout CAD; circuit optimisation; delays; digital integrated circuits; integrated circuit layout; search problems; IC layout; controlled sizing techniques; gate delay; incremental path search algorithm; longest combinational paths selection; path resizing; performance optimization; power/area constraints; CMOS process; Central Processing Unit; Circuit optimization; Circuit synthesis; Design optimization; Electronic mail; Propagation delay; Robots; Robustness; Timing;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.705219
