Author :
Amutha, C. ; Ramya, M. ; Subashini, C.
Abstract :
Notice of Violation of IEEE Publication Principles
???A Novel Co-Design Approach for Soft Error Mitigation for Embedded System???
by C. Amutha, M. Ramya, C. Subashini
in the Proceedings of the International Conference on Emerging Trends in Electrical Engineering and Energy Management (ICETEEEM), December 2012, pp. 267-270
After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE???s Publication Principles.
This paper contains large portions of text and figures copied verbatim from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission.
Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:
???Compiler-Directed Soft Error Mitigation for Embedded Systems???
by Antonio Martinez-Alvarez, Sergio A. Cuenca-Asensi, Felipe Restrepo-Calle, Francisco R. Pinto, Hipolito Guzman-Miranda, Miguel A. Aguirre
in the IEEE Transactions on Dependable and Secure Computing, Vol 9, No. 2, March 2012, pp. 159-172
The protection of processor-based systems to mitigate the harmful effect of transient faults. This paper proposes an Depth packet inspection methodology for facilitating the design of fault tolerant embedded systems, the packet inspection is possible in compressed data and thereby achieve high fault coverage in accuracy and speed. The methodology is supported by an infrastructure that hardware and software soft errors mitigation techniques in order to best satisfy both usual design constraints permits to easily combine hardware and software dependability requirements. It is based on a FPGA architecture that facilitates the implementation of software-based techniques, providi- g a uniform isolated from target hardening core that allows the automatic generation of protected source code.
Keywords :
embedded systems; fault tolerant computing; field programmable gate arrays; hardware-software codesign; inspection; program compilers; source coding; FPGA architecture; automatic protected source code generation; codesign approach; data compression; depth packet inspection methodology; design constraints; fault tolerant embedded systems; hardware dependability requirements; hardware soft error mitigation techniques; high fault coverage; processor-based systems protection; software dependability requirements; software soft error mitigation techniques; software-based techniques; target hardening core; transient faults; Fault tolerance; hardware software co design; single event upset-SEU; soft error;
