Title :
Low power, small die-size PLL using semi-digital storage instead of big loop filter capacitance
Author :
Dietl, Markus ; Sareen, Puneet
Author_Institution :
Texas Instrum., Clock & Timing products, Freising, Germany
Abstract :
Conventional low bandwidth Phase lock loop uses an external Capacitor together with a big on chip ripple capacitor. A new architecture of a Phase lock loop is proposed which eliminates the need for an external capacitor. Also the value of the on chip capacitor is reduced drastically, reducing the chip size. The PLL architecture proposed uses very low power.
Keywords :
capacitors; digital storage; low-power electronics; phase locked loops; PLL architecture; big loop filter capacitance; big on chip ripple capacitor; external capacitor; low power PLL; semidigital storage; small die-size PLL; Capacitors; Charge pumps; Computer architecture; Microprocessors; Phase locked loops; Voltage control; Voltage-controlled oscillators; Low power; Phase lock loop; Real time clock;
Conference_Titel :
Networked Embedded Systems for Enterprise Applications (NESEA), 2010 IEEE International Conference on
Conference_Location :
Suzhou
Print_ISBN :
978-1-4244-9178-0
Electronic_ISBN :
978-1-4244-9176-6
DOI :
10.1109/NESEA.2010.5678055
