Title :
Wafer level detecting of Idd failures in CMOS ASICs using liquid crystal techniques
Author :
Ma, Jun ; Haley, Mark W. ; Mitchell, Todd W. ; Sanchez, Ivan
Author_Institution :
VLSI Technology, Inc., San Antonio, TX, USA
Abstract :
Simple techniques using liquid crystal and different power-up schemes to locate the failures in CMOS ASICs on the wafer level are described. These techniques are simple and efficient, and are used to locate defects and floating nodes which cause Idd failures at wafer sort. Wafer level defect reduction and prototype debugging are successfully performed on parts in which Idd source location is difficult
Keywords :
CMOS integrated circuits; application specific integrated circuits; failure analysis; fault location; integrated circuit testing; liquid crystal devices; CMOS ASIC; Idd failures; Idd source location; defect location; failure location; floating nodes location; liquid crystal techniques; power-up schemes; prototype debugging; wafer level defect reduction; Application specific integrated circuits; Debugging; Failure analysis; Liquid crystal devices; Liquid crystals; Manufacturing; Optical polarization; Product design; Prototypes; Temperature;
Conference_Titel :
University/Government/Industry Microelectronics Symposium, 1993., Proceedings of the Tenth Biennial
Conference_Location :
Research Triangle Park, NC
Print_ISBN :
0-7803-0990-1
DOI :
10.1109/UGIM.1993.297060
