3D interconnection for ultra-dense multichip modules

The increasing density of the interconnection of ASICs (application-specific integrated circuits) and memories is discussed. It is demonstrated that the interconnections of ASICs require the utilization of thin-film multilayers. However, since ASICs are interconnected in an extremely dense manner, the relative area occupied by the memories increases substantially, and currently amounts to approximately 50%. The 3-D interconnection technology allows reduction of the occupied area by a factor of 7 or 8 and thus yielded ultradense multichip modules. This interconnection approach consists of interconnecting the bare chips not in the xy plane but along the z axis. The interconnection process entails interconnecting the four sides of the cube formed by stacking n chips (n =8 by 10) on top of one another. To do so, the chips are individually interconnected on a thin film identical to a TAB (tape automated bonding) film by means of gold wires prior to cubing. This technique also substantially improves the high-frequency behavior of ICs. An application consisting of a cube of eight stacked 256-kb static random-access memories is being developed