Title :
The DMOS consisting of channel region defined by LOCOS (LOCOS-DMOS): a new process/device technology for low on-resistance power MOSFET
Author :
Tokura, Norihito ; Takahashi, Shigeki ; Hara, Kunihiko
Author_Institution :
Nippondenso Co., Ltd., Aichi, Japan
Abstract :
A novel process/device technology for a low on-resistance power MOSFET, namely, a DMOS consisting of a channel region defined by LOCOS (LOCOS-DMOS), is described. The vertical channel structure is formed not by the trench etching technique, but by a combination of local oxidation of silicon (LOCOS) and diffusion self-alignment (DSA) using LOCOS oxide film as a double diffusion mask. The results of process/device modeling of a 12-μm microcell and two-dimensional numerical simulations indicate an approximately 40% improvement in on-resistance compared with conventional planar-DMOS under the same conditions of cell pitch and 50-V blocking voltage. The formation of a hollow structure by LOCOS is verified by the two-dimensional process simulation. The LOCOS-DMOS technology promises a great improvement in power loss for MOSFETs operated under high-power switching
Keywords :
MOS integrated circuits; insulated gate field effect transistors; integrated circuit technology; oxidation; power integrated circuits; power transistors; semiconductor device models; semiconductor process modelling; LOCOS oxide film; LOCOS-DMOS; Si; diffusion self-alignment; double diffusion mask; high-power switching; hollow structure; low on-resistance power MOSFET; microcell; modeling; power loss; process/device technology; two-dimensional numerical simulations; vertical channel structure; Degradation; Etching; Immune system; MOSFET circuits; Microcell networks; Numerical simulation; Power MOSFET; Semiconductor films; Very large scale integration; Voltage;
Conference_Titel :
Power Semiconductor Devices and ICs, 1993. ISPSD '93., Proceedings of the 5th International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-1313-5
DOI :
10.1109/ISPSD.1993.297124
