Junction and dielectrically isolated lateral ESTs for power ICs

Conventional and dual-channel dielectrically isolated (DI) and junction-isolated (JI) lateral emitter switched thyristors (LESTs) have been fabricated using the reduced surface field (RESURF) principle. The breakdown voltage for then JI LEST was found to be greater than 700 V, while that for the DI LEST was up to 500 V depending on the silicon drift layer and isolating oxide layer thickness. The DI devices exhibited marginally higher forward voltage drops compared to the corresponding JI LESTs. The switching time for the DI structures was found to be an order of magnitude faster than for the JL LESTs, which 2D device simulation shows to be due to elimination of injection of carriers into the substrate. The dual-channel LESTs has a higher forward voltage drop than the conventional structures and exhibited high-voltage current saturation behavior. Dual-channel LEST structures with different anode structure, i.e., the conventional LEST, the anode shorted LEST and the hybrid Schottky LEST, were also examined