DocumentCode
1895934
Title
Accelerating pattern matching for DPI
Author
Mu, Jun ; Sezer, Sakir ; Douglas, Gareth ; Burns, Dwayne ; Garcia, Emi ; Hutton, Mike ; Cackovic, Kevin
Author_Institution
ECIT Institute, Queen¿s University, Belfast, UK
fYear
2007
fDate
26-29 Sept. 2007
Firstpage
83
Lastpage
86
Abstract
Pattern matching in network applications is characterized by intensive computation. In conventional hardware accelerating methods, performance versus cost is a trade-off. In this paper, we proposed a new Hash-CAM hybrid architecture using state-of-the-art FPGA technology that is customized for a given pattern matching problem for DPI.
Keywords
Acceleration; CADCAM; Circuits; Computer aided manufacturing; Costs; Data security; Field programmable gate arrays; Hardware; Information security; Pattern matching;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2007 IEEE International
Conference_Location
Hsin Chu, Taiwan
Print_ISBN
978-1-4244-1592-2
Electronic_ISBN
978-1-4244-1593-9
Type
conf
DOI
10.1109/SOCC.2007.4545432
Filename
4545432
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