Design rules to avoid tunnel cracking in VLSI interconnects during process flow

Author

Brillet, H. ; Orain, S. ; Fiori, Vincent ; Dupeux, M. ; Braccini, M.

Author_Institution

STMicroelectronics, Crolles, France

fYear

2005

fDate

18-20 April 2005

Firstpage

248

Lastpage

253

Abstract

A failure analysis based on an energy approach is used to study a two metal level structure in VLSI interconnects. The failure scenario of a channel cracking at the interface low-k /TaNTa is treated for the first level. A finite element FE model has been developed which shows the impact of the layout and the process on the stress level and interface decohesion probability in this structure. In addition, some general design rules are deduced from these calculations to avert crack propagation in interconnects.

Keywords

VLSI; design engineering; failure analysis; finite element analysis; fracture; integrated circuit interconnections; tantalum compounds; TaNTa; VLSI interconnect; channel cracking; crack propagation; energy approach; failure analysis; finite element model; interface decohesion probability; layout impact; low-k /TaNTa interface; process flow; stress level; tunnel cracking; two metal level structure; Capacitive sensors; Cooling; Etching; Inorganic materials; Performance evaluation; Temperature; Testing; Thermomechanical processes;

fLanguage

English

Publisher

ieee

Conference_Titel

Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2005. EuroSimE 2005. Proceedings of the 6th International Conference on

Print_ISBN

0-7803-9062-8

Type

conf

DOI

10.1109/ESIME.2005.1502809

Filename

1502809