Predicting hysteretic oscillations in over-temperature protection of a power IC using transient electrothermal circuit simulation

A transient electrothermal circuit simulation methodology combining ANSYS transient FEA (finite element analysis) simulation (using active control elements) with steady-state SPICE simulations has been demonstrated. The hysteretic oscillation period of OTSD (over-temperature shutdown) protection circuitry in a power IC was accurately predicted over a power input range of 1.8 to 3.6 W and for periods ranging from 1.3 to 0.1 s, respectively. Simulation further showed that temperature gradients during cooling were small compared to those during heating transients. The peak junction temperature in the power IC studied was found to exhibit a 10 to 17°C overshoot at the shutdown limit, depending on the power input. Further studies suggest that on-chip thermal protection should be located within 50 μm of a dominant heat source to minimize the magnitude of this overshoot. The effects of ambient conditions on OTSD operation are shown to be greatest for low-power inputs resulting in long oscillation periods