Design of ultra low power CML MUXs and latches with forward body bias

In this paper, a novel Forward Body Biasing (FBB) circuit is proposed for ultra low power Current Mode Logic (CML) MUXs and Latches. Through the proposed clocked-power FBB circuit, the supply voltage VDD and the dc-level of the differential inputs can be reduced significantly, while maintaining the original swing of differential outputs. Our architecture can reach power saving up to 60%, and 50% in average with slight penalty of area and frequency. The design methodology and performance analysis for FBB CML MUXs and Latches are presented. The same design concept can also be extended to logic circuits composed of differential input pairs.