Low-power high-performance FinFET sequential circuits

Scaling of single-gate bulk MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the leakage power. Double-gate MOSFET technologies mitigate this limitation by providing an excellent control over a thin silicon body with two electrically coupled gates. FinFET is the most attractive choice among the double-gate transistor architectures because of the self alignment of the two gates and the similarity of the fabrication steps to the existing standard CMOS technology. In this paper, new sequential circuits based on independent-gate FinFETs are proposed to simultaneously reduce the power consumption and the circuit area. With the proposed independently biased double-gate FinFET sequential circuits, the active power consumption, the leakage power, the clock power, and the circuit area are reduced by up to 46%, 42%, 26%, and 20%, respectively, as compared to the standard sequential circuits with tied-gate FinFETs.