Title :
Stochastic glitch elimination considering path correlation
Author :
Kim, Youse ; Zang, Naeun ; Kim, Juho
Author_Institution :
Department of Computer Science and Engineering, Sogang University, Seoul, Korea
Abstract :
A new power optimization by stochastic glitch estimation and removal is proposed in this paper. As the first step of our method, glitch occurrence probability is computed using statistical static timing analysis considering path correlation. Then, path balancing by resizing is applied to remove glitches that are unnecessary signal transitions.
Keywords :
Circuits; Computer science; Delay estimation; Energy consumption; Power dissipation; Power engineering and energy; Power engineering computing; Probability; Stochastic processes; Timing;
Conference_Titel :
SOC Conference, 2007 IEEE International
Conference_Location :
Hsin Chu, Taiwan
Print_ISBN :
978-1-4244-1592-2
Electronic_ISBN :
978-1-4244-1593-9
DOI :
10.1109/SOCC.2007.4545451
