DocumentCode
1896441
Title
Characterization of Upset-induced Degradation of Error-mitigated Highspeed I/O´s Using Fault Injection
Author
Rezgui, Sana ; Swift, Gary M. ; Lesea, Austin
Author_Institution
Xilinx Inc., San Jose
fYear
2005
fDate
19-23 Sept. 2005
Abstract
Fault-injection experiments on Virtex-II FPGAs quantify failure and degradation modes in I/O channels incorporating triple modular redundancy (TMR). With increasing frequency (to 100 MHz), full TMR under both I/O standards investigated shows more configuration bits have a measurable performance effect.
Keywords
fault simulation; field programmable gate arrays; logic design; performance evaluation; reconfigurable architectures; redundancy; configuration bits; degradation mode; error-mitigated highspeed I/O channels; failure mode; fault injection; triple modular redundancy; upset-induced degradation; Circuit faults; Degradation; Field programmable gate arrays; Frequency; Laboratories; Logic testing; Propulsion; Redundancy; Single event transient; Voltage; Fault Injection; field programmable gate arrays (FPGAs); upset mitigation; upset simulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Radiation and Its Effects on Components and Systems, 2005. RADECS 2005. 8th European Conference on
Conference_Location
Cap d´Agde
ISSN
0379-6566
Print_ISBN
978-0-7803-9502-2
Electronic_ISBN
0379-6566
Type
conf
DOI
10.1109/RADECS.2005.4365642
Filename
4365642
Link To Document