Title :
A 65nm low power 2T1D embedded DRAM with leakage current reduction
Author :
Chang, Mu-Tien ; Huang, Po-Tsang ; Hwang, Wei
Author_Institution :
Department of Electronics Engineering & Institute of Electronics, and Microelectronics and Information Systems Research Center, National Chiao-Tung University, HsinChu 300, Taiwan
Abstract :
Gain cell memories feature high speed, low power, and high density, which are suitable for SoC designs. In this paper, low power techniques to reduce leakage currents for 2T1D gain cell memory array are presented. For each memory cell, p-type gated diode storage device is applied. In addition, footer power gating and foot driver are applied on each memory word. Simulation results show that the proposed 2T1D memory array structure has 97.7% and 80% standby power reduction over typical 2T1D and typical 3T1D memory array, respectively. All the simulation results are based on Predictive Technology Model (PTM) 65nm CMOS bulk technology.
Keywords :
CMOS technology; Capacitance; Diodes; Energy consumption; Foot; Leakage current; Logic devices; Predictive models; Random access memory; Voltage;
Conference_Titel :
SOC Conference, 2007 IEEE International
Conference_Location :
Hsin Chu, Taiwan
Print_ISBN :
978-1-4244-1592-2
Electronic_ISBN :
978-1-4244-1593-9
DOI :
10.1109/SOCC.2007.4545459
