DocumentCode :
1896810
Title :
Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding
Author :
Chen, Xiaolin ; Canagarajah, Nishan ; Yanez, Jose L Nunez ; Vitulli, Raffaele
Author_Institution :
Department of Electrical and Electronic Engineering, University of Bristol, UK
fYear :
2007
fDate :
26-29 Sept. 2007
Firstpage :
251
Lastpage :
254
Abstract :
In this paper we present a novel hardware architecture for context-based statistical lossless image compression, as part of a dynamically reconfigurable architecture for universal lossless compression. A gradient-adjusted prediction and context modeling algorithm is adapted to a pipelined scheme for low complexity and high throughput. Our proposed system improves image compression ratio while keeping low hardware complexity. This system is designed for a Xilinx Virtex4 FPGA core and optimized to achieve a 123 MHz clock frequency for real-time processing.
Keywords :
Arithmetic; Clocks; Context modeling; Design optimization; Field programmable gate arrays; Frequency; Hardware; Image coding; Reconfigurable architectures; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOC Conference, 2007 IEEE International
Conference_Location :
Hsin Chu, Taiwan
Print_ISBN :
978-1-4244-1592-2
Electronic_ISBN :
978-1-4244-1593-9
Type :
conf
DOI :
10.1109/SOCC.2007.4545469
Filename :
4545469
Link To Document :
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