DocumentCode
1896835
Title
A programmable FFT/IFFT/Windowing processor for multi standard DSL applications
Author
Baireddy, Vijayavardhan ; Khasnis, Himamshu ; Mundhada, Rajesh
Author_Institution
Texas Instruments, India, Pvt Ltd., Bangalore, Karnataka, India
fYear
2007
fDate
26-29 Sept. 2007
Firstpage
255
Lastpage
258
Abstract
A programmable 64-4096 point FFT/IFFT/Windowing processor for DSL applications is discussed. Dynamic scaling, computation restructuring in terms of radix-2 butterfly and clustered computation power down methods are presented. The single multiplier based 360MHz design occupies 0.38sqmm of area in 90nm process and consumes 19.8mW of dynamic power for a 4096 point computation.
Keywords
CMOS technology; Computer architecture; Computer buffers; DSL; Hardware; Instruments; Modems; Read-write memory; Signal processing; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2007 IEEE International
Conference_Location
Hsin Chu, Taiwan
Print_ISBN
978-1-4244-1592-2
Electronic_ISBN
978-1-4244-1593-9
Type
conf
DOI
10.1109/SOCC.2007.4545470
Filename
4545470
Link To Document