Predictable system interconnects through accurate early wire characterization

This work envisions a feasible solution for faster convergence towards a flexible and robust design alternative for the global wires encountered in a SoC. The application of the proposed approach based on early wire characterization to the global interconnects of a Network-on-Chip (NoC), clearly shows that the novel method can converge the design to close-to-target solution in very few steps, if not meet the target directly. Furthermore, the irregular solution provided by the traditional flow causes the self and coupling capacitances and therefore the total capacitance vary in a wide spectrum, whereas, the regular structures dictated by the proposed approach result in a uniform distribution of the capacitances.