FPGA-based implementation of binary input compressive sensing decoder

Binary input compressive sensing (BiCS) is the kernel of seamless rate adaptation system. But the high complexity of the decoding algorithms has prevented this technique from being applied to practical communication systems. In this paper, a decoder with serial architecture is proposed and implemented in FPGA. Two specific optimizations are employed to improve the throughput of the decoder. First, we take advantage of the configurable aspect ratio of the block RAM in FPGA to make the decoder work fully pipelined. Second, the ping pang operation is adopted to increase the hardware utilization efficiency. When the clock frequency is 300MHz and the number of iterations is 10, the maximum throughput of the decoder is about 29.4Mbps that reaches the range of communication rate in modern wireless networks.