Centip3De: A 64-Core, 3D Stacked Near-Threshold System

Author

Dreslinski, Ronald G. ; Fick, David ; Giridhar, B. ; Gyouho Kim ; Sangwon Seo ; Fojtik, Matthew ; Satpathy, Sudhir ; Yoonmyung Lee ; Daeyeon Kim ; Liu, Nian ; Wieckowski, Michael ; Chen, Gang ; Sylvester, Dennis ; Blaauw, D. ; Mudge, Trevor

Author_Institution

Univ. of Michigan, Ann Arbor, MI, USA

Volume

33

Issue

2

fYear

2013

fDate

March-April 2013

Firstpage

8

Lastpage

16

Abstract

Centip3De uses the synergy between 3D integration and near-threshold computing to create a reconfigurable system that provides both energy-efficient operation and techniques to address single-thread performance bottlenecks. The original Centip3De design is a seven-layer 3D stacked design with 128 cores and 256 Mbytes of DRAM. Silicon results show a two-layer, 64-core system in 130-nm technology, which achieved an energy efficiency of 3,930 DMIPS/W.

Keywords

DRAM chips; elemental semiconductors; energy conservation; multiprocessing systems; performance evaluation; power aware computing; reconfigurable architectures; silicon; 3D integration; Centip3De; DRAM; Si; energy-efficient operation; near-threshold computing; reconfigurable system; seven-layer 3D stacked design; single-thread performance bottlenecks; size 130 nm; two-layer 64-core system; Integrated circuit interconnections; Low power electronics; Power system management; Random access memory; Three dimensional displays; Threshold voltage; Through-silicon vias; Centip3De; advanced technologies; hardware; integrated circuits; low-power design; power management; types and design styles;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2013.4

Filename

6415891