3DMemory — Memory usage analysis tool

Author

Schonberger, Alex ; Hofmann, Klaus

Author_Institution

Integrated Electron. Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany

fYear

2014

fDate

15-19 June 2014

Firstpage

81

Lastpage

85

Abstract

Die-stacking technology is opening up new options for memory system design. Through silicon vias (TSV) provide a configurable interface between memory and processing unit and allow a high bandwidth. System performance can be increased significantly by a sophisticated DRAM architecture design. This paper presents a framework providing a design recommendation for memory based on application execution data. The analysis approach can be adapted for different system configurations and applications. In this work a single-core execution of JPEG2000 algorithm for different picture sizes is analyzed with the tool.

Keywords

DRAM chips; integrated circuit design; three-dimensional integrated circuits; 3D memory; DRAM architecture design; JPEG2000 algorithm; application execution data; die-stacking technology; memory system design; memory usage analysis tool; picture sizes; processing unit; single-core execution; system performance; through silicon vias; Computational modeling; Data structures; Memory architecture; Monitoring; Random access memory; Three-dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Embedded Computing (MECO), 2014 3rd Mediterranean Conference on

Conference_Location

Budva

Print_ISBN

978-1-4799-4827-7

Type

conf

DOI

10.1109/MECO.2014.6862663

Filename

6862663