Title :
Graph transformation for communication minimization using retiming
Author :
Sheliga, Michael ; Yu, Zhihong ; Chen, Fei ; Sha, Edwin H M
Author_Institution :
Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
fDate :
31 May-3 Jun 1998
Abstract :
Nested loops are normally the most time intensive tasks in computer algorithms. These loops often include multiple dependencies between arrays that impose communication constraints when used in multiprocessor systems. These dependencies may be between dependent arrays (loop dependencies), or between independent arrays (data dependencies). In this paper, reducing the communication caused by data and loop dependencies for perfect nested loops is explored. It is shown that for a given partition data dependencies may be treated as a specialized form of loop dependencies. Once this is done, previous results on scalable loop tiling can be used to calculate the final total communication. Next, the effects of changing the partition for both loop and data communication are examined. Using these results, the optimal partition for a number of cases is examined. Results are shown which illustrate the efficiency of the system as well as the savings achieved
Keywords :
application specific integrated circuits; delays; graph theory; multiprocessing systems; parallel architectures; timing; communication constraints; communication minimization; computer algorithms; data dependencies; dependent arrays; graph transformation; independent arrays; loop dependencies; multiprocessor systems; perfect nested loops; retiming; scalable loop tiling; Adaptive control; Computer science; Data communication; Delay; Digital signal processing; Image processing; Multiprocessing systems; Parallel architectures; Programmable control; Signal processing algorithms;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.705248