Low-resistivity noble integrated clustered electrode (NICE) WSi/sub x/ polycide and its application to a deep sub-quarter micron CMOS

Author

Jeong Soo Byun ; Ji-Soo Park ; Byung Hak Lee ; Dong-Kyun Sohn ; Jin Won Park ; Jae Jeong Kim ; Jeong Mo Hwang

Author_Institution

Adv. Tech. Lab., LG Semicon Co. Ltd., Cheongju, South Korea

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

119

Lastpage

122

Abstract

This paper is aimed at suggesting a new technique satisfying the requirement of future devices using a clustered platform, named NICE WSix. It consists of sequential deposition of in-situ doped poly and SiH/sub 2/Cl/sub 2/ (DCS)-based WSix, forming a WSix/poly-Si stacked gate. The resistivity of NICE WSix was 36 /spl mu//spl Omega//spl middot/cm after thermal annealing, which is three times lower than that of conventional WSix (Conv.WSix). Moreover, the thermal stability was found to be excellent. We have successfully applied this technology for 1 Giga-bit DRAM.

Keywords

CMOS memory circuits; DRAM chips; ULSI; annealing; circuit stability; integrated circuit metallisation; tungsten compounds; 1 Gbit; DRAM; WSi; clustered platform; deep sub-quarter micron CMOS; noble integrated clustered electrode; polycide; resistivity; sequential deposition; stacked gate; thermal annealing; thermal stability; Amorphous materials; Annealing; CMOS process; Conductivity; Electrodes; Metallization; Random access memory; Temperature; Thermal resistance; Thermal stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.649478

Filename

649478