Title :
Gate to channel shorts in PMOS devices: effects on logic gate failures
Author :
Sayeed, M. Shaheen ; Mourad, Samiha
Author_Institution :
Dept. of Electr. Eng., Santa Clara Univ., CA, USA
fDate :
31 May-3 Jun 1998
Abstract :
Gate to channel shorts via oxide layers have an enormous effect on VLSI circuits and may render devices useless. However, there is no sure way of detecting and locating such faults due to their random nature. In order to test VLSI circuits, a working model is essential in the event a gate oxide short occurs. A model for gate oxide shorts in PMOS transistors is presented in this paper and used to determine the behavior of digital gates in the presence of these shorts. Except when the short resistance is very low, the failure is not detectable by voltage testing and current or delay testing is necessary
Keywords :
MOS logic circuits; VLSI; delays; fault diagnosis; integrated circuit testing; logic gates; logic testing; PMOS devices; VLSI circuits; current testing; delay testing; fault location; gate to channel shorts; logic gate failures; oxide layers; short resistance; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Logic devices; Logic gates; MOS devices; MOSFETs; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.705249
