DocumentCode :
1897772
Title :
Arithmetic core generation using bit heaps
Author :
Brunie, Nicolas ; de Dinechin, Florent ; Istoan, Matei ; Sergent, Guillaume ; Illyes, Kinga ; Popa, Bogdan
fYear :
2013
fDate :
2-4 Sept. 2013
Firstpage :
1
Lastpage :
8
Abstract :
A bit heap is a data structure that holds the unevaluated sum of an arbitrary number of bits, each weighted by some power of two. Most advanced arithmetic cores can be viewed as involving one or several bit heaps. We claim here that this point of view leads to better global optimization at the algebraic level, at the circuit level, and in terms of software engineering. To demonstrate it, a generic software framework is introduced for the definition and optimization of bit heaps. This framework, targeting DSP-enabled FPGAs, is developed within the open-source FloPoCo arithmetic core generator. Its versatility is demonstrated on several examples: multipliers, complex multipliers, polynomials, and discrete cosine transform.
Keywords :
data structures; digital arithmetic; digital signal processing chips; field programmable gate arrays; logic design; optimisation; public domain software; DSP-enabled FPGA; advanced arithmetic cores; algebraic level; arbitrary number of bits; arithmetic core generation; bit heaps; circuit level; data structure; generic software framework; global optimization; open-source FloPoCo arithmetic core generator; software engineering; unevaluated sum; Adders; Digital signal processing; Field programmable gate arrays; Generators; Optimization; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on
Conference_Location :
Porto
Type :
conf
DOI :
10.1109/FPL.2013.6645544
Filename :
6645544
Link To Document :
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