Enhancing circuit performance under a multiple-phase clocking scheme

For general synchronous circuits, input and output data are stored in latches or flip-flops which are triggered by the clock signal, so the clock period is a measurement of circuit performance. Previous studies on this issue are restricted by the assumption of triggering all inputs at the same clock phase. We propose a new method to reduce the clock period without the above assumption. The proposed method allows the existence of clock skew and produces a better clock period. The improvement in circuit performance is demonstrated by our experimental results