Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration

Field-Programmable Gate Array (FPGA) systems are increasingly susceptible to radiation-induced Single Event Upsets (SEUs). Application circuits are most commonly protected from SEUs using Triple Modular Redundancy (TMR) and scrubbing to eliminate configuration memory errors. This paper focuses on implementing circuits that recover from SEUs within a specified maximum recovery period, a practical requirement not previously addressed. We develop a recovery time model, describe a scalable reconfiguration control network, and investigate the performance of a representative TMR system implemented using our approach. The results demonstrate that modular reconfiguration eliminate configuration errors more responsively and using less energy than scrubbing. However, these benefits are achieved at the cost of additional area, minor speed penalties, and greater design complexity.