Title :
Vertical NPN bipolar junction transistors fabricated in silicon-on-sapphire
Author :
Cartagena, E.N. ; Offord, B.W. ; Walker, H.
Author_Institution :
US Naval Ocean Syst. Center, San Diego, CA, USA
Abstract :
Vertical NPN bipolar junction transistors were fabricated on DSPE (double solid-phase epitaxy) improved SOS (silicon-on-sapphire) using conventional furnace anneals. Transistors with an effective emitter area of 40 square microns were measured for current gain (βDC) and Early voltage (VA). Functional devices with βDC values of up to 70, V A values of 40 volts, and fT values of 1 gigahertz were recorded. A thin SOS film (0.27 micron) was regrown with DSPE process to reduce the microtwin defect concentration. A common emitter characteristic curve for a BJT (bipolar junction transistor) fabricated in DSPE improved SOS is shown. It can be seen from this sample that the effects of enhanced diffusion along dislocations causing emitter-collector shorts are minimized by utilizing the DSPE process prior to epitaxy deposition
Keywords :
bipolar transistors; semiconductor epitaxial layers; semiconductor technology; semiconductor-insulator boundaries; solid phase epitaxial growth; 40 V; DSPE; Early voltage; NPN transistors; SOS; Si-Al2O3; bipolar junction transistors; common emitter characteristic curve; current gain; double SPE; double solid-phase epitaxy; epitaxy deposition; fT; furnace anneals; vertical bipolar transistors; Annealing; Epitaxial growth; Furnaces; Implants; Leakage current; Low voltage; Oceans; Silicon on insulator technology; Solid state circuits; Transistors;
Conference_Titel :
SOI Conference, 1991. Proceedings, 1991., IEEE International
Conference_Location :
Vail Valley, CO
Print_ISBN :
0-7803-0184-6
DOI :
10.1109/SOI.1991.162887
