Hardware-efficient implementation of a Femtocell/Macrocell interference-mitigation technique for high-performance LTE-based systems

Author

Font-Bach, Oriol ; Bartzoudis, Nikolaos ; Payaro, Miquel ; Pascual-Iserte, Antonio

Author_Institution

Centre Tecnol. de Telecomunicacions de Catalunya (CTTC), Barcelona, Spain

fYear

2013

fDate

2-4 Sept. 2013

Firstpage

1

Lastpage

4

Abstract

This paper presents the FPGA design of an interference-aware digital front end tailored for heterogeneous multi-cell LTE-based systems. A resource-optimized RTL architecture has been implemented and validated under realistic operating conditions using the GEDOMIS^® testbed. The parallelization and concurrent resource utilization of the joint synchronization and interference detection processing blocks is covered with low-level details.

Keywords

Long Term Evolution; femtocellular radio; field programmable gate arrays; interference suppression; logic design; radiofrequency interference; synchronisation; FPGA design; GEDOMIS testbed; concurrent resource utilization; femtocell/macrocell interference-mitigation technique; hardware-efficient implementation; heterogeneous multicell LTE-based systems; high-performance LTE-based systems; interference detection processing blocks; interference-aware digital front end; parallelization; realistic operating conditions; resource-optimized RTL architecture; synchronization; Field programmable gate arrays; Finite impulse response filters; Interference; OFDM; Real-time systems; Resource management; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on

Conference_Location

Porto

Type

conf

DOI

10.1109/FPL.2013.6645585

Filename

6645585