Dependence of Jitter Accumulation on Line Codes for Clock Recovery with Minimal Filtering

Line codes for clock recovery with minimal filtering are investigated. First, it is discussed that a 4T processing is preferable to conventional 4T/2T processing for a 1B4B/3B4B code from the standpoint of jitter reduction. Then 2B/4B codes are proposed where 3T and 1T processings are applicable. Dependence of jitter accumulation on the above schemes is tested in chains of repeaters. It is shown that these new codes can not only simplify hardware but also lead to improved jitter characteristic as compared with existing schemes.