Dynamic effects in SOI MOSFET´s

The use of SOI (silicon-on-insulator) and conventional bulk MOSFETs by circuit designers is similar in a wide range of functions for logic purposes. Differences may appear when asynchronous design is used, due to floating body effects. The consequences of direct coupling between drain and source of a MOSFET in the OFF-state are discussed, and the characterization of this effect for various SOI technologies is presented. Two mechanisms are proposed to explain the results: a capacitive coupling between drain and floating body, which corresponds to a drain to source coupling when the floating body follows the source potential; and a dynamic bipolar effect in which the base current is constituted by the gate oxide charge in accumulated mode. This effect leads to a parasitic drain to source discharge, which can result in an upset in a SRAM memory cell or in a dynamic latch. It is found that a careful design must be done if functions like dynamic or static latch are needed