Operation scheduling in VLSI circuit design

The crucial step involved in the transforming of a behavioral specification given at the algorithmic level into a RTL structure (high-level synthesis) is the operation scheduling, which basically is the task of defining the timing of the operation execution. A new algorithm solving the scheduling problem is presented and compared with the best ones published. The scheduling algorithm is integrated in a software environment (`ASCAM´) reading VHDL behavioural description, giving an optimal architecture and translating it in the input format of a silicon compiler, which performs the final steps of the design