Design of a Process Tolerant Cell Library for Regular Structures using Symbolic Layout and Hierarchical Compaction

A method is presented to design cell libraries, using a symbolic layout editor and a hierarchical compaction algorithm with automatic terminal fitting. In contrast to language based procedural layout, this technique guarantees correctness and easy updatability to new circuit techniques and layout rules. It can be applied to all regular hierarchical layout structures where constrained cells have to be designed. Once the library is established it can be used over and over again with different personality matrices for fast generation of correct layout.