An Interactive Layout Design System with Real-Time Logical Verification and Parameter Extraction

This paper presents an interactive design system, which meets the special requirements of cell based design methods, like gate array, bipolar analogue standard cell and particularly transistor array approaches concerning layout verification. A real-time logical extraction tool is provided, which is integrated into the interactive layout editor of the system. Hierarchical circuit verification is supported, which is based on a functional and logical description of the layout components. In addition, special verification tools for bipolar transistor array design applications are presented.