Title :
Integration challenges of 0.1 μm CMOS Cu/low-k interconnects
Author :
Yu, K.C. ; Werking, J. ; Prindle, C. ; Kiene, M. ; Ng, M.-F. ; Wilson, B. ; Singhal, A. ; Stephens, T. ; Huang, F. ; Sparks, T. ; Aminpur, M. ; Linville, J. ; Denning, D. ; Brennan, B. ; Shahvandi, I. ; Wang, C. ; Flake, J. ; Chowdhury, R. ; Svedberg, L.
Author_Institution :
Digital DNA Labs., Motorola Inc., Austin, TX, USA
Abstract :
The integration challenges of a low-k dielectric (k < 3) to form multi-level Cu interconnects for the next generation 0.1 μm CMOS technology are presented. Process improvements to overcome these challenges are highlighted which include etchfront control, resist poisoning, high aspect ratio metallization, and improved CMP planarity. The maturity of this technology has been demonstrated through high yield of a 4MB SRAM test vehicle.
Keywords :
CMOS integrated circuits; copper; dielectric thin films; integrated circuit interconnections; 0.1 micron; 4 MB; CMOS technology; CMP planarity; Cu; Cu multi-level interconnect; SRAM; etch front control; high aspect ratio metallization; low-k dielectric; process integration; resist poisoning; Ash; Atherosclerosis; CMOS technology; Capacitance; Chemistry; Dielectric constant; Etching; Isolation technology; Metrology; Resists;
Conference_Titel :
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International
Print_ISBN :
0-7803-7216-6
DOI :
10.1109/IITC.2002.1014870
