Determination of back interface state distribution in fully-depleted SOI MOSFETs

Two techniques based on observable DC MOSFET device parameters are described that can be used to extract the interface state density at the back Si-SiO₂ interface as a function of position in the bandgap. These techniques can be incorporated into a DC MOSFET test program. A set of I_D-V_GS curves is shown for a thin (200 nm, type 1) fully depleted SIMOX (separation by implanted oxygen) p⁺-poly-gate n-MOSFET as substrate bias varies from -15 to 0 V. Over this substrate voltage range, the back interface passes from accumulation through depletion into inversion. Also shown is the extracted distribution of back interface states below midgap as determined from both the threshold and subthreshold slope data from this n-MOSFET