Title :
A manufacturable copper/low-k SiOC/SiCN process technology for 90 nm-node high performance eDRAM
Author :
Higashi, K. ; Nakamura, N. ; Miyajima, Hiroki ; Satoh, S. ; Kojima, A. ; Abe, J. ; Nagahata, K. ; Tatsumi, T. ; Tabuchi, K. ; Hasegawa, T. ; Kawashima, H. ; Arakawa, S. ; Matsunaga, N. ; Shibata, H.
Author_Institution :
Syst. LSI Res. & Dev. Center, Toshiba Corp. Semicond. Co., Japan
Abstract :
In this paper, we describe the Cu/low-k (k < 3) dual-damascene process integration targeting for 90 nm-node (0.28 μm pitch) high performance embedded DRAM devices. A stable and well-controlled dual-damascene structure was realized both by using newly developed stacked mask process (S-MAP) and a low-damage resist ashing process. Problems and solutions for resist poisoning due to the stopper-SiCN layer and capping-SiO2 layer are investigated. We also demonstrated a notable via chain yield (with 2.9 M vias) by applying low-k PE-CVD SiOC/SiCN dielectrics.
Keywords :
DRAM chips; copper; dielectric thin films; integrated circuit interconnections; plasma CVD coatings; silicon compounds; 90 nm; Cu-SiOC-SiCN; capping SiO2 layer; copper/low-k SiOC/SiCN process technology; dual damascene structure; embedded DRAM device; low-k PECVD SiOC/SiCN dielectric; multilevel interconnect; process integration; resist ashing process; resist poisoning; stacked mask process; stopper SiCN layer; via chain yield; Chemicals; Computer hacking; Copper; Etching; Helium; Leakage current; Manufacturing processes; Moisture; Resists; Wiring;
Conference_Titel :
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International
Print_ISBN :
0-7803-7216-6
DOI :
10.1109/IITC.2002.1014873
