Title :
Wafer process and issue of through electrode in Si wafer using Cu damascene for three dimensional chip stacking
Author :
Hoshino, Masataka ; Yonemura, Hitoshi ; Tomisaka, M. ; Fujii, Tomonori ; Sunohara, Masahiro ; Takahashi, Koichi
Author_Institution :
Electron. Syst. Integration Technol. Res. Dept., Assoc. of Super-Adv. Electron. Technol., Ibaraki, Japan
Abstract :
The elemental technologies of three-dimensional (3D) LSI chip stacking are described. Chip based stacking technology is under development that includes thorough electrode formation, wafer thinning, chip stacking, and inspection and testing. In order to make over 2,000 bumps on a 10 mm-square chip, the thorough electrode and micro bump dimensions are 10 μm square, 20 μm pitch. Chips are thinned up to 50 μm for high-density packaging. This technology aims to develop the technologies to overcome the performance bottleneck of electronic systems. We summarize the update of this project and discuss wafer process issue.
Keywords :
VLSI; copper; integrated circuit interconnections; integrated circuit packaging; large scale integration; sputter etching; wafer bonding; 10 micron; 10 mm; 20 micron; 3D LSI chip stacking; 50 micron; Cu; Cu damascene; Cu fillings; LSI interconnection process; RIE; Si; Si wafer processing; electrode formation; high-density packaging; inspection; micro bump formation; reactive ion etching; testing; three-dimensional chip stacking; through hole etching; via filling; wafer thinning; Atherosclerosis; Dry etching; Electrodes; Electronics packaging; Filling; Integrated circuit interconnections; Large scale integration; Stacking; Surface morphology; System-on-a-chip;
Conference_Titel :
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International
Print_ISBN :
0-7803-7216-6
DOI :
10.1109/IITC.2002.1014892
