Design of 32-bit RISC processor and efficient verification

Author

Jeong, Geun-young ; Park, Ju-Sung

Author_Institution

Dept. of Electron. Eng., Pusan Nat. Univ., South Korea

Volume

2

fYear

2003

fDate

6-6 July 2003

Firstpage

222

Abstract

The design and verification of a 32-bit general- purpose microprocessor, which is compatible with ARM? RISC core, is described. In the architectural point of view, the processor has 3-stage pipeline, 6 register banks, 32-bit ALU, and 4-cycle MAC. The core described here was designed by latch base for low power and low complexity. Its functional operation was verified by comparison the results of logic simulation with those of the commercial simulator. Each instruction and its random combinations were all tested. The core was implemented by FPGA to check its proper operation for various applications, such as ADPCM (G.721-speech coding), SOLA (voice speed variation), MP3 decoding. It carried out successfully those algorithms.

Keywords

field programmable gate arrays; logic simulation; microprocessor chips; reduced instruction set computing; 3-stage pipeline; 32-bit ALU; 32-bit general-purpose microprocessor; 4-cycle MAC; 6 register bank; ARM7 RISC core; FPGA; instruction combination; logic simulation; random combination;

fLanguage

English

Publisher

ieee

Conference_Titel

Science and Technology, 2003. Proceedings KORUS 2003. The 7th Korea-Russia International Symposium on

Conference_Location

Ulsan, South Korea

Print_ISBN

89-7868-617-6

Type

conf

Filename

1222609