Title :
Mechanisms of stress-induced voids in multi-level Cu interconnects
Author :
Park, Ryung-Lyul ; Hah, Sang-Rok ; Park, Chan-Geun ; Jeong, Dong-Kwon ; Son, Hong-Seong ; Oh, Hyeok-Sang ; Chung, Ju-Hyuk ; Nam, Jeong-Lim ; Park, Kwang-Mycon ; Byun, Jae-Dong
Author_Institution :
Korea Univ., Seoul, South Korea
Abstract :
One of the most serious problems in Cu-based multilevel integration is the failure in stacked vias caused by stress-induced voids. In this paper, the failure mechanism of the stacked via resistance is evaluated by analyzing the effects of the conditions of deposition and annealing in electroplated-Cu (EP-Cu) and the damascene structure scheme in a 64-bit RISC microprocessor with 7 copper layers. The stress-induced void is closely related to the stress change and the volume shrinkage of EP-Cu generated during deposition and annealing. The stacked via failures can be effectively suppressed with the application of two-step deposition and annealing in the EP-Cu process at the relatively low temperature of about 200°C and the single damascene scheme for the layer of Via-5/Metal-6.
Keywords :
ULSI; annealing; copper; electroplated coatings; electroplating; failure analysis; integrated circuit interconnections; integrated circuit reliability; internal stresses; microprocessor chips; voids (solid); 200 degC; 64 bit; Cu; Cu-based multilevel interconnect; RISC microprocessor; ULSI devices; annealing conditions; annealing temperature; damascene structure; deposition conditions; failure mechanism; single damascene scheme; stacked via failure; stress change; stress-induced voids; two-step deposition; via resistance; volume shrinkage; Annealing; Copper; Electric resistance; Electrical resistance measurement; Failure analysis; Large scale integration; Microprocessors; Reduced instruction set computing; Stress; Temperature;
Conference_Titel :
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International
Print_ISBN :
0-7803-7216-6
DOI :
10.1109/IITC.2002.1014910
