Title :
A methodology for the interconnect performance evaluation of 2D and 3D processors with memory
Author :
Chandra, Girish ; Kapur, Pawan ; Saraswat, Krishna C.
Author_Institution :
Stanford Univ., CA, USA
Abstract :
Stochastic wire length distribution models often overlook the presence of a large amount of on-chip memory, treating it as random logic. Based on layout considerations for the memory, a methodology for interconnect performance evaluation is proposed that takes the memory into account. It is shown that not taking the complete model can lead to erroneous results. The benefits of 3D integration are then evaluated with different possible arrangements of memory on different active layers.
Keywords :
integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; integrated memory circuits; microprocessor chips; 2D processors; 3D integration; 3D processors; active layers; interconnect model; interconnect performance evaluation; memory layout considerations; on-chip memory; random logic; stochastic wire length distribution models; Conductors; Distributed computing; Logic; Microprocessors; Performance analysis; Routing; Stochastic processes; Wire; Wiring;
Conference_Titel :
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International
Print_ISBN :
0-7803-7216-6
DOI :
10.1109/IITC.2002.1014921
