An efficient design of IPCR(image processing cache register) for wavelet transform

An efficient algorithm for integer wavelet transform is proposed to reduce the hardware complexity by using lifting-based scheme. We designed an IPCR (image processing cache register) in VHDL for the proposed algorithm. The architecture of wavelet transform is composed of image processor, IPCR, original frame store, and redundant frame store. For this work only the IPCR block was implemented in FPGA platform. The designed IPCR contains two chains and one window block. This architecture has been synthesized using Max+PLUSII. The estimated cells of the proposed IPCR are 64 logic cells, and the estimated operation frequency is 47.84 MHz. We compared the proposed architecture with S-wavelet transform, assuming an 8/spl times/8 block horizontal computation. Our proposed architecture needs only 92 logic cells including one IPCR and two adders comparing with 192 logic cells of S-wavelet transform necessary eight registers and adders.